Information

Section Number Title Page
33.1.4 VREF Signal Descriptions...........................................................................................................................661
33.2 Memory Map and Register Definition..........................................................................................................................662
33.2.1 VREF Trim Register (VREF_TRM)............................................................................................................662
33.2.2 VREF Status and Control Register (VREF_SC)..........................................................................................663
33.3 Functional Description..................................................................................................................................................664
33.3.1 Voltage Reference Disabled, SC[VREFEN] = 0.........................................................................................665
33.3.2 Voltage Reference Enabled, SC[VREFEN] = 1..........................................................................................665
33.4 Initialization/Application Information..........................................................................................................................666
Chapter 34
Programmable Delay Block (PDB)
34.1 Introduction...................................................................................................................................................................667
34.1.1 Features........................................................................................................................................................667
34.1.2 Implementation............................................................................................................................................668
34.1.3 Back-to-back Acknowledgement Connections............................................................................................669
34.1.4 Block Diagram.............................................................................................................................................669
34.1.5 Modes of Operation.....................................................................................................................................671
34.2 PDB Signal Descriptions..............................................................................................................................................671
34.3 Memory Map and Register Definition..........................................................................................................................671
34.3.1 Status and Control Register (PDBx_SC).....................................................................................................672
34.3.2 Modulus Register (PDBx_MOD).................................................................................................................675
34.3.3 Counter Register (PDBx_CNT)...................................................................................................................675
34.3.4 Interrupt Delay Register (PDBx_IDLY)......................................................................................................676
34.3.5 Channel n Control Register 1 (PDBx_CHnC1)...........................................................................................676
34.3.6 Channel n Status Register (PDBx_CHnS)...................................................................................................677
34.3.7 Channel n Delay 0 Register (PDBx_CHnDLY0)........................................................................................678
34.3.8 Channel n Delay 1 Register (PDBx_CHnDLY1)........................................................................................678
34.3.9 Pulse-Out n Enable Register (PDBx_POEN)...............................................................................................679
34.3.10 Pulse-Out n Delay Register (PDBx_POnDLY)...........................................................................................679
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
26 Freescale Semiconductor, Inc.