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fast load transitions. In addition, do not modify the clock source
in the MCG module, the module clock enables in the SIM, or
any clock divider registers.
To reenter Normal Run mode, clear RUNM. The PMSTAT register is a read-only status
register that can be used to determine when the system has completed an exit to RUN
mode. When PMSTAT=RUN, the system is in run regulation and the MCU can run at
full speed in any clock mode. If a higher execution frequency is desired, poll the
PMSTAT register until it is set to RUN when returning from VLPR mode.
VLPR mode also provides the option to return to run regulation if any interrupt occurs.
Implement this option by setting Low-Power Wakeup On Interrupt (LPWUI) in the
PMCTRL register. Any reset always causes an exit from VLPR and returns the device to
RUN mode after the MCU exits its reset flow. The RUNM bits are cleared by hardware
on any interrupt when LPWUI is set or on any reset.
14.4.4 Wait modes
This device contains two different wait modes:
• Wait
• Very-Low Power Wait (VLPW)
14.4.4.1 WAIT mode
WAIT mode is entered when the ARM core enters the Sleep-Now or Sleep-On-Exit
modes while SLEEDEEP is cleared. The ARM CPU enters a low-power state in which it
is not clocked, but peripherals continue to be clocked provided they are enabled. Clock
gating to the peripheral is enabled via the SIM..
When an interrupt request occurs, the CPU exits WAIT mode and resumes processing in
RUN mode, beginning with the stacking operations leading to the interrupt service
routine.
A system reset will cause an exit from WAIT mode, returning the device to normal RUN
mode.
14.4.4.2 Very-Low-Power Wait (VLPW) mode
VLPW is entered by the entering the Sleep-Now or Sleep-On-Exit mode while
SLEEPDEEP is cleared and the MCU is in VLPR mode.
Chapter 14 System Mode Controller
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 273