Information

PMC_LVDSC2 field descriptions (continued)
Field Description
5
LVWIE
Low-Voltage Warning Interrupt Enable
Enables hardware interrupt requests for LVWF.
0 Hardware interrupt disabled (use polling)
1 Request a hardware interrupt when LVWF = 1
4–2
Reserved
This read-only field is reserved and always has the value zero.
1–0
LVWV
Low-Voltage Warning Voltage Select
Selects the LVW trip point voltage (V
LVW
). The actual voltage for the warning depends on
LVDSC1[LVDV].
00 Low trip point selected (V
LVW
= V
LVW1
)
01 Mid 1 trip point selected (V
LVW
= V
LVW2
)
10 Mid 2 trip point selected (V
LVW
= V
LVW3
)
11 High trip point selected (V
LVW
= V
LVW4
)
15.5.3 Regulator Status And Control register (PMC_REGSC)
The PMC contains an internal voltage regulator. The voltage regulator design uses a
bandgap reference that is also available through a buffer as input to certain internal
peripherals, such as the CMP and ADC. The internal regulator provides a status bit
(REGONS) indicating the regulator is in run regulation.
NOTE
This register is reset on Chip Reset Not VLLS and by reset
types that trigger Chip Reset not VLLS. See the Reset section
for more information.
Address: PMC_REGSC is 4007_D000h base + 2h offset = 4007_D002h
Bit 7 6 5 4 3 2 1 0
Read 0
BGEN
ACKISO REGONS
Reserved BGBE
Write w1c
Reset
0 0 0 0 0 1 0 0
PMC_REGSC field descriptions
Field Description
7–5
Reserved
This read-only field is reserved and always has the value zero.
4
BGEN
Bandgap Enable In VLPx Operation
Table continues on the next page...
Memory map and register descriptions
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
284 Freescale Semiconductor, Inc.