Information

Section Number Title Page
35.4.13 Software output control................................................................................................................................782
35.4.14 Deadtime insertion.......................................................................................................................................784
35.4.15 Output mask.................................................................................................................................................787
35.4.16 Fault control.................................................................................................................................................788
35.4.17 Polarity control.............................................................................................................................................791
35.4.18 Initialization.................................................................................................................................................792
35.4.19 Features priority...........................................................................................................................................792
35.4.20 Channel trigger output.................................................................................................................................793
35.4.21 Initialization trigger......................................................................................................................................794
35.4.22 Capture Test mode.......................................................................................................................................796
35.4.23 DMA............................................................................................................................................................797
35.4.24 Dual Edge Capture mode.............................................................................................................................798
35.4.25 Quadrature Decoder mode...........................................................................................................................805
35.4.26 BDM mode...................................................................................................................................................810
35.4.27 Intermediate load..........................................................................................................................................811
35.4.28 Global time base (GTB)...............................................................................................................................813
35.5 Reset overview..............................................................................................................................................................814
35.6 FTM Interrupts..............................................................................................................................................................816
35.6.1 Timer Overflow Interrupt.............................................................................................................................816
35.6.2 Channel (n) Interrupt....................................................................................................................................816
35.6.3 Fault Interrupt..............................................................................................................................................816
Chapter 36
Periodic Interrupt Timer (PIT)
36.1 Introduction...................................................................................................................................................................817
36.1.1 Block diagram..............................................................................................................................................817
36.1.2 Features........................................................................................................................................................818
36.2 Signal description..........................................................................................................................................................818
36.3 Memory map/register description.................................................................................................................................819
36.3.1 PIT Module Control Register (PIT_MCR)..................................................................................................820
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 29