Information

16.3.1 LLWU Pin Enable 1 register (LLWU_PE1)
LLWU_PE1 contains the field to enable and select the edge detect type for the external
wakeup input pins LLWU_P3-LLWU_P0.
NOTE
This register is reset on Chip Reset not VLLS and by reset
types that trigger Chip Reset not VLLS. It is unaffected by reset
types that do not trigger Chip Reset not VLLS. See the
Introduction details for more information.
Address: LLWU_PE1 is 4007_C000h base + 0h offset = 4007_C000h
Bit 7 6 5 4 3 2 1 0
Read
WUPE3 WUPE2 WUPE1 WUPE0
Write
Reset
0 0 0 0 0 0 0 0
LLWU_PE1 field descriptions
Field Description
7–6
WUPE3
Wakeup Pin Enable For LLWU_P3
Enables and configures the edge detection for the wakeup pin.
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
5–4
WUPE2
Wakeup Pin Enable For LLWU_P2
Enables and configures the edge detection for the wakeup pin.
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
3–2
WUPE1
Wakeup Pin Enable For LLWU_P1
Enables and configures the edge detection for the wakeup pin.
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
1–0
WUPE0
Wakeup Pin Enable For LLWU_P0
Enables and configures the edge detection for the wakeup pin.
00 External input pin disabled as wakeup input
Table continues on the next page...
Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
292 Freescale Semiconductor, Inc.