Information

LLWU_FILT2 field descriptions (continued)
Field Description
3–0
FILTSEL
Filter Pin Select
Selects 1 out of the 16 wakeup pins to be muxed into the filter.
0000 Select LLWU_P0 for filter
... ...
1111 Select LLWU_P15 for filter
16.3.11 LLWU Reset Enable register (LLWU_RST)
LLWU_RST is a control register that is used to enable/disable the digital filter for the
external pin detect and RESET pin.
NOTE
This register is reset on Chip Reset not VLLS and by reset
types that trigger Chip Reset not VLLS. It is unaffected by reset
types that do not trigger Chip Reset not VLLS. See the
Introduction details for more information.
Address: LLWU_RST is 4007_C000h base + Ah offset = 4007_C00Ah
Bit 7 6 5 4 3 2 1 0
Read 0
LLRSTE RSTFILT
Write
Reset
0 0 0 0 0 0 1 0
LLWU_RST field descriptions
Field Description
7–2
Reserved
This read-only field is reserved and always has the value zero.
1
LLRSTE
Low-Leakage Mode RESET Enable
This bit must be set to allow the device to be reset while in a low-leakage power mode. On devices where
Reset is not a dedicated pin, the RESET pin must also be enabled in the explicit port mux control.
0 RESET pin not enabled as a leakage mode exit source
1 RESET pin enabled as a low leakage mode exit source
0
RSTFILT
Digital Filter On RESET Pin
Enables the digital filter for the RESET pin during LLS, VLLS3, VLLS2, or VLLS1 modes.
0 Filter not enabled
1 Filter enabled
Chapter 16 Low-Leakage Wakeup Unit (LLWU)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 305