Information

18.2 Memory Map / Register Definition
This design was meant to be as small as possible. To help achieve this, the crossbar
switch contains no memory-mapped registers for configuring.
18.3 Functional Description
18.3.1 General operation
When a master accesses the crossbar switch the access is immediately taken. If the
targeted slave port of the access is available, then the access is immediately presented on
the slave port. Single-clock, or -zero-wait state, accesses are possible through the
crossbar. If the targeted slave port of the access is busy or parked on a different master
port, the requesting master simply sees wait states inserted until the targeted slave port
can service the master's request. The latency in servicing the request depends on each
master's priority level and the responding peripheral's access time.
Because the crossbar switch appears to be just another slave to the master device, the
master device has no knowledge of whether it actually owns the slave port it is targeting.
While the master does not have control of the slave port it is targeting, it simply waits.
A master is given control of the targeted slave port only after a previous access to a
different slave port completes, regardless of its priority on the newly targeted slave port.
This prevents deadlock from occurring when:
• A higher priority master has:
• An outstanding request to one slave port that has a long response time and
• A pending access to a different slave port, and
• A lower priority master is also making a request to the same slave port as the pending
access of the higher priority master.
After the master has control of the slave port it is targeting, the master remains in control
of that slave port until it gives up the slave port by running an IDLE cycle or by leaving
that slave port for its next access.
The master could also lose control of the slave port if another higher priority master
makes a request to the slave port; however, if the master is running a fixed- or undefined-
length burst transfer it retains control of the slave port until that transfer completes. Based
on MGPCR[AULB], the master either retains control of the slave port when doing
undefined length incrementing burst transfers or loses the bus to a higher priority master.
Memory Map / Register Definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
314 Freescale Semiconductor, Inc.