Information

• The first region defines a number of registers providing control functions
• The second region corresponds to the local transfer control descriptor memory
Each channel requires a 32-byte transfer control descriptor for defining the desired data
movement operation. The channel descriptors are stored in the local memory in
sequential order: channel 0, channel 1,... channel 3 . Each TCDn definition is presented as
11 registers of 16 or 32 bits.
Reading reserved bits in a register returns the value of zero. Writes to reserved bits in a
register are ignored. Reading or writing a reserved memory location generates a bus
error.
DMA memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_8000 Control Register (DMA_CR) 32 R/W 0000_0000h 21.3.1/340
4000_8004 Error Status Register (DMA_ES) 32 R 0000_0000h 21.3.2/342
4000_800C Enable Request Register (DMA_ERQ) 32 R/W 0000_0000h 21.3.3/344
4000_8014 Enable Error Interrupt Register (DMA_EEI) 32 R/W 0000_0000h 21.3.4/345
4000_8018 Clear Enable Error Interrupt Register (DMA_CEEI) 8
W
(always
reads
zero)
00h 21.3.5/346
4000_8019 Set Enable Error Interrupt Register (DMA_SEEI) 8
W
(always
reads
zero)
00h 21.3.6/347
4000_801A Clear Enable Request Register (DMA_CERQ) 8
W
(always
reads
zero)
00h 21.3.7/348
4000_801B Set Enable Request Register (DMA_SERQ) 8
W
(always
reads
zero)
00h 21.3.8/349
4000_801C Clear DONE Status Bit Register (DMA_CDNE) 8
W
(always
reads
zero)
00h 21.3.9/350
4000_801D Set START Bit Register (DMA_SSRT) 8
W
(always
reads
zero)
00h
21.3.10/
351
Table continues on the next page...
Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
336 Freescale Semiconductor, Inc.