Information

NOTE
For proper operation, writes to the CR register must be
performed only when the DMA channels are inactive; that is,
when TCDn_CSR[ACTIVE] bits are cleared.
Address: DMA_CR is 4000_8000h base + 0h offset = 4000_8000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CX
ECX
0
EMLM
CLM
HALT
HOE
0
ERCA
EDBG
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CR field descriptions
Field Description
31–18
Reserved
This read-only field is reserved and always has the value zero.
17
CX
Cancel Transfer
0 Normal operation
1 Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The
cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after
the cancel has been honored. This cancel retires the channel normally as if the minor loop was
completed.
16
ECX
Error Cancel Transfer
0 Normal operation
1 Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and
force the minor loop to finish. The cancel takes effect after the last write of the current read/write
sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer,
ECX treats the cancel as an error condition, thus updating the ES register and generating an optional
error interrupt.
15–8
Reserved
This read-only field is reserved and always has the value zero.
7
EMLM
Enable Minor Loop Mapping
0 Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
1 Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES
field. The individual enable fields allow the minor loop offset to be applied to the source address, the
destination address, or both. The NBYTES field is reduced when either offset is enabled.
6
CLM
Continuous Link Mode
0 A minor loop channel link made to itself goes through channel arbitration before being activated
again.
1 A minor loop channel link made to itself does not go through channel arbitration before being
activated again. Upon minor loop completion, the channel activates again if that channel has a minor
loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets
and restarts the next minor loop.
5
HALT
Halt DMA Operations
Table continues on the next page...
Chapter 21 Direct Memory Access Controller (eDMA)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 341