Information

DMA_ERQ field descriptions (continued)
Field Description
3
ERQ3
Enable DMA Request 3
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
2
ERQ2
Enable DMA Request 2
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
1
ERQ1
Enable DMA Request 1
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
0
ERQ0
Enable DMA Request 0
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
21.3.4 Enable Error Interrupt Register (DMA_EEI)
The EEI register provides a bit map for the 4 channels to enable the error interrupt signal
for each channel. The state of any given channel’s error interrupt enable is directly
affected by writes to this register; it is also affected by writes to the SEEI and CEEI. The
{S,C}EEI are provided so the error interrupt enable for a single channel can easily be
modified without the need to perform a read-modify-write sequence to the EEI register.
The DMA error indicator and the error interrupt enable flag must be asserted before an
error interrupt request for a given channel is asserted to the interrupt controller.
Address: DMA_EEI is 4000_8000h base + 14h offset = 4000_8014h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
EEI3 EEI2 EEI1 EEI0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_EEI field descriptions
Field Description
31–4
Reserved
This read-only field is reserved and always has the value zero.
3
EEI3
Enable Error Interrupt 3
Table continues on the next page...
Chapter 21 Direct Memory Access Controller (eDMA)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 345