Information

Section Number Title Page
43.1.3 DSPI Configurations....................................................................................................................................957
43.1.4 Modes of Operation.....................................................................................................................................958
43.2 DSPI signal descriptions...............................................................................................................................................960
43.2.1 PCS0/SS — Peripheral Chip Select/Slave Select........................................................................................960
43.2.2 PCS1 – PCS3 — Peripheral Chip Selects 1 – 3...........................................................................................960
43.2.3 PCS4 — Peripheral Chip Select 4................................................................................................................961
43.2.4 SIN — Serial Input......................................................................................................................................961
43.2.5 SOUT — Serial Output................................................................................................................................961
43.2.6 SCK — Serial Clock....................................................................................................................................961
43.3 Memory Map/Register Definition.................................................................................................................................961
43.3.1 DSPI Module Configuration Register (SPIx_MCR)....................................................................................963
43.3.2 DSPI Transfer Count Register (SPIx_TCR)................................................................................................966
43.3.3 DSPI Clock and Transfer Attributes Register (In Master Mode) (SPIx_CTARn)......................................966
43.3.4 DSPI Clock and Transfer Attributes Register (In Slave Mode) (SPIx_CTARn_SLAVE)..........................971
43.3.5 DSPI Status Register (SPIx_SR)..................................................................................................................972
43.3.6 DSPI DMA/Interrupt Request Select and Enable Register (SPIx_RSER)..................................................975
43.3.7 DSPI PUSH TX FIFO Register In Master Mode (SPIx_PUSHR)...............................................................977
43.3.8 DSPI PUSH TX FIFO Register In Slave Mode (SPIx_PUSHR_SLAVE)..................................................979
43.3.9 DSPI POP RX FIFO Register (SPIx_POPR)...............................................................................................979
43.3.10 DSPI Transmit FIFO Registers (SPIx_TXFRn)...........................................................................................980
43.3.11 DSPI Receive FIFO Registers (SPIx_RXFRn)............................................................................................981
43.4 Functional description...................................................................................................................................................981
43.4.1 Start and Stop of DSPI transfers..................................................................................................................982
43.4.2 Serial Peripheral Interface (SPI) configuration............................................................................................983
43.4.3 DSPI baud rate and clock delay generation.................................................................................................986
43.4.4 Transfer formats...........................................................................................................................................989
43.4.5 Continuous Serial Communications Clock..................................................................................................994
43.4.6 Slave Mode Operation Constraints..............................................................................................................995
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
36 Freescale Semiconductor, Inc.