Information

DMA_TCDn_CITER_ELINKNO field descriptions (continued)
Field Description
14–0
CITER
Current Major Iteration Count
This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current major loop count for the channel.
It is decremented each time the minor loop is completed and updated in the transfer control descriptor
memory. After the major iteration count is exhausted, the channel performs a number of operations (e.g.,
final source and destination address calculations), optionally generating an interrupt to signal channel
completion before reloading the CITER field from the beginning iteration count (BITER) field.
NOTE: When the CITER field is initially loaded by software, it must be set to the same value as that
contained in the BITER field.
NOTE: If the channel is configured to execute a single service request, the initial values of BITER and
CITER should be 0x0001.
21.3.28 TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD_DLASTSGA)
Addresses: TCD0_DLASTSGA is 4000_8000h base + 1018h offset = 4000_9018h
TCD1_DLASTSGA is 4000_8000h base + 1038h offset = 4000_9038h
TCD2_DLASTSGA is 4000_8000h base + 1058h offset = 4000_9058h
TCD3_DLASTSGA is 4000_8000h base + 1078h offset = 4000_9078h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DLASTSGA
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset.•
DMA_TCDn_DLASTSGA field descriptions
Field Description
31–0
DLASTSGA
Destination last address adjustment or the memory address for the next transfer control descriptor to be
loaded into this channel (scatter/gather).
If (TCDn_CSR[ESG] = 0) then
• Adjustment value added to the destination address at the completion of the major iteration count.
This value can apply to restore the destination address to the initial value or adjust the address to
reference the next data structure.
else
• This address points to the beginning of a 0-modulo-32-byte region containing the next transfer
control descriptor to be loaded into this channel. This channel reload is performed as the major
iteration count completes. The scatter/gather address must be 0-modulo-32-byte, else a
configuration error is reported.
Chapter 21 Direct Memory Access Controller (eDMA)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 367