Information

address spaces remains important. However, the microarchitecture of the eDMA also
factors significantly into the resulting metric.
21.4.4.1 Peak transfer rates
The peak transfer rates for several different source and destination transfers are shown in
the following tables. These tables assume:
• Internal SRAM can be accessed with zero wait-states when viewed from the system
bus data phase
• All internal peripheral bus reads require two wait-states, and internal peripheral bus
writes three wait-states, when viewed from the system bus data phase
• All internal peripheral bus accesses are 32-bits in size
This table presents a peak transfer rate comparison.
Table 21-101. eDMA peak transfer rates (Mbytes/sec)
System Speed,
Width
Internal SRAM-to-
Internal SRAM
32b internal peripheral bus-
to-
Internal SRAM
Internal SRAM-to-
32b internal peripheral bus
66.7 MHz, 32b 133.3 66.7 53.3
83.3 MHz, 32b 166.7 83.3 66.7
100.0 MHz, 32b 200.0 100.0 80.0
133.3 MHz, 32b 266.7 133.3 106.7
150.0 MHz, 32b 300.0 150.0 120.0
Internal-SRAM-to-internal-SRAM transfers occur at the core's datapath width. For all
transfers involving the internal peripheral bus, 32-bit transfer sizes are used. In all cases,
the transfer rate includes the time to read the source plus the time to write the destination.
21.4.4.2 Peak request rates
The second performance metric is a measure of the number of DMA requests that can be
serviced in a given amount of time. For this metric, assume that the peripheral request
causes the channel to move a single internal peripheral bus-mapped operand to/from
internal SRAM. The same timing assumptions used in the previous example apply to this
calculation. In particular, this metric also reflects the time required to activate the
channel.
Functional description
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
378 Freescale Semiconductor, Inc.