Information

is retiring the channel. The TCD.e_sg would be set in the programmer’s model, but it
would be unclear whether the actual scatter/gather request was honored before the
channel retired.
Two methods for this coherency model are shown in the following subsections. Method 1
has the advantage of reading the major.linkch field and the e_sg bit with a single read.
For both dynamic channel linking and scatter/gather requests, the TCD local memory
controller forces the TCD.major.e_link and TCD.e_sg bits to zero on any writes to a
channel’s TCD.word7 if that channel’s TCD.done bit is set indicating the major loop is
complete.
NOTE
The user must clear the TCD.done bit before writing the
TCD.major.e_link or TCD.e_sg bits. The TCD.done bit is
cleared automatically by the eDMA engine after a channel
begins execution.
21.5.7.3.1 Method 1 (channel not using major loop channel linking)
For a channel not using major loop channel linking, the coherency model described here
may be used for a dynamic scatter/gather request.
When the TCD.major.e_link bit is zero, the TCD.major.linkch field is not used by the
eDMA. In this case, the TCD.major.linkch bits may be used for other purposes. This
method uses the TCD.major.linkch field as a TCD indentification (ID).
1. When the descriptors are built, write a unique TCD ID in the TCD.major.linkch field
for each TCD associated with a channel using dynamic scatter/gather.
2. Write 1b to theTCD.d_req bit.
Should a dynamic scatter/gather attempt fail, setting the d_req bit will prevent a
future hardware activation of this channel. This stops the channel from executing
with a destination address (daddr) that was calculated using a scatter/gather address
(written in the next step) instead of a dlast final offest value.
3. Write theTCD.dlast_sga field with the scatter/gather address.
4. Write 1b to the TCD.e_sg bit.
5. Read back the 16 bit TCD control/status field.
6. Test the TCD.e_sg request status and TCD.major.linkch value:
If e_sg = 1b, the dynamic link attempt was successful.
Chapter 21 Direct Memory Access Controller (eDMA)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 393