Information
Section Number Title Page
45.8.6 Match address registers................................................................................................................................1140
45.8.7 Modem feature.............................................................................................................................................1140
45.8.8 IrDA minimum pulse width.........................................................................................................................1141
45.8.9 Clearing 7816 wait timer (WT, BWT, CWT) interrupts..............................................................................1141
45.8.10 Legacy and reverse compatibility considerations........................................................................................1142
Chapter 46
Synchronous Audio Interface (SAI)
46.1 Introduction...................................................................................................................................................................1143
46.1.1 Features........................................................................................................................................................1143
46.1.2 Block diagram..............................................................................................................................................1143
46.1.3 Modes of operation......................................................................................................................................1144
46.2 External signals.............................................................................................................................................................1145
46.3 Memory map and register definition.............................................................................................................................1146
46.3.1 SAI Transmit Control Register (I2Sx_TCSR).............................................................................................1147
46.3.2 SAI Transmit Configuration 1 Register (I2Sx_TCR1)................................................................................1150
46.3.3 SAI Transmit Configuration 2 Register (I2Sx_TCR2)................................................................................1150
46.3.4 SAI Transmit Configuration 3 Register (I2Sx_TCR3)................................................................................1152
46.3.5 SAI Transmit Configuration 4 Register (I2Sx_TCR4)................................................................................1153
46.3.6 SAI Transmit Configuration 5 Register (I2Sx_TCR5)................................................................................1154
46.3.7 SAI Transmit Data Register (I2Sx_TDRn)..................................................................................................1155
46.3.8 SAI Transmit FIFO Register (I2Sx_TFRn).................................................................................................1155
46.3.9 SAI Transmit Mask Register (I2Sx_TMR)..................................................................................................1156
46.3.10 SAI Receive Control Register (I2Sx_RCSR)...............................................................................................1156
46.3.11 SAI Receive Configuration 1 Register (I2Sx_RCR1)..................................................................................1159
46.3.12 SAI Receive Configuration 2 Register (I2Sx_RCR2)..................................................................................1160
46.3.13 SAI Receive Configuration 3 Register (I2Sx_RCR3)..................................................................................1161
46.3.14 SAI Receive Configuration 4 Register (I2Sx_RCR4)..................................................................................1162
46.3.15 SAI Receive Configuration 5 Register (I2Sx_RCR5)..................................................................................1163
46.3.16 SAI Receive Data Register (I2Sx_RDRn)...................................................................................................1164
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 41