Information

Section Number Title Page
46.3.17 SAI Receive FIFO Register (I2Sx_RFRn)...................................................................................................1164
46.3.18 SAI Receive Mask Register (I2Sx_RMR)...................................................................................................1165
46.3.19 SAI MCLK Control Register (I2Sx_MCR).................................................................................................1166
46.3.20 SAI MCLK Divide Register (I2Sx_MDR)..................................................................................................1167
46.4 Functional description...................................................................................................................................................1167
46.4.1 SAI clocking................................................................................................................................................1167
46.4.2 SAI resets.....................................................................................................................................................1169
46.4.3 Synchronous modes.....................................................................................................................................1169
46.4.4 Frame sync configuration.............................................................................................................................1170
46.4.5 Data FIFO....................................................................................................................................................1171
46.4.6 Word mask register......................................................................................................................................1172
46.4.7 Interrupts and DMA requests.......................................................................................................................1173
Chapter 47
General-Purpose Input/Output (GPIO)
47.1 Introduction...................................................................................................................................................................1175
47.1.1 Features........................................................................................................................................................1175
47.1.2 Modes of operation......................................................................................................................................1175
47.1.3 GPIO signal descriptions.............................................................................................................................1176
47.2 Memory map and register definition.............................................................................................................................1177
47.2.1 Port Data Output Register (GPIOx_PDOR).................................................................................................1180
47.2.2 Port Set Output Register (GPIOx_PSOR)....................................................................................................1180
47.2.3 Port Clear Output Register (GPIOx_PCOR)................................................................................................1181
47.2.4 Port Toggle Output Register (GPIOx_PTOR).............................................................................................1181
47.2.5 Port Data Input Register (GPIOx_PDIR).....................................................................................................1182
47.2.6 Port Data Direction Register (GPIOx_PDDR).............................................................................................1183
47.3 Functional description...................................................................................................................................................1183
47.3.1 General-purpose input..................................................................................................................................1183
47.3.2 General-purpose output................................................................................................................................1183
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
42 Freescale Semiconductor, Inc.