Information

MCGOUTCLK
MCGIRCLK
MCGFFCLK
DCOOUT
/(24,25,26,...,55)
Phase
Detector
Charge
Pump
Internal
Filter
VCO
VCOOUT
PLL
Multipurpose Clock Generator (MCG)
VDIV0
Lock
Clock
Monitor
IRCLKEN
PLLS
LOLS0 LOCK0
Detector
/ 2
5
IREFST
FLL
DMX32
MCGFLLCLK
Crystal Oscillator
FRDIV
n=0-7
/ 2
n
Internal
Reference
Slow Clock
Fast Clock
Clock
Generator
PRDIV0
LOLIE0
Sync
Auto Trim Machine
IRCST
PLLST
CLKST
ATMS
SCTRIM
SCFTRIM
FCTRIM
ATMST
IREFSTEN
OSCINIT0
EREFS0
HGO0
RANGE0
External
DRS
Clock
Valid
Peripheral BUSCLK
PLLCLKEN0
IRCSCLK
IRCS
CLKSCLKS
DCO
LP
Filter
/(1,2,3,4,5....,25)
IREFS
STOP
CLKS
PLLCLKEN0
IREFS
PLLS
MCG Crystal Oscillator
Enable Detect
External Reference Clock
RTC
Oscillator
OSCSEL
OSCSELCLK
n=0-7
/ 2
n
FLTPRSRV
LOCS0
MCGPLLCLK
CME0
LOCRE0
CME1
LOCRE1
LOCS1
Figure 24-1. Multipurpose Clock Generator (MCG) block diagram
Introduction
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
430 Freescale Semiconductor, Inc.