Information

MCG_C4 field descriptions (continued)
Field Description
The DRS bits select the frequency range for the FLL output, DCOOUT. When the LP bit is set, writes to
the DRS bits are ignored. The DRST read field indicates the current frequency range for DCOOUT. The
DRST field does not update immediately after a write to the DRS field due to internal synchronization
between clock domains. See the DCO Frequency Range table for more details.
00 Encoding 0 — Low range (reset default).
01 Encoding 1 — Mid range.
10 Encoding 2 — Mid-high range.
11 Encoding 3 — High range.
4–1
FCTRIM
Fast Internal Reference Clock Trim Setting
FCTRIM
1
controls the fast internal reference clock frequency by controlling the fast internal reference
clock period. The FCTRIM bits are binary weighted, that is, bit 1 adjusts twice as much as bit 0.
Increasing the binary value increases the period, and decreasing the value decreases the period.
If an FCTRIM[3:0] value stored in nonvolatile memory is to be used, it is your responsibility to copy that
value from the nonvolatile memory location to this register.
0
SCFTRIM
Slow Internal Reference Clock Fine Trim
SCFTRIM
2
controls the smallest adjustment of the slow internal reference clock frequency. Setting
SCFTRIM increases the period and clearing SCFTRIM decreases the period by the smallest amount
possible.
If an SCFTRIM value stored in nonvolatile memory is to be used, it is your responsibility to copy that value
from the nonvolatile memory location to this bit.
1. A value for FCTRIM is loaded during reset from a factory programmed location .
2. A value for SCFTRIM is loaded during reset from a factory programmed location .
24.3.5 MCG Control 5 Register (MCG_C5)
Address: MCG_C5 is 4006_4000h base + 4h offset = 4006_4004h
Bit 7 6 5 4 3 2 1 0
Read 0
PLLCLKEN0
PLLSTEN0 PRDIV0
Write
Reset
0 0 0 0 0 0 0 0
MCG_C5 field descriptions
Field Description
7
Reserved
This read-only field is reserved and always has the value zero.
6
PLLCLKEN0
PLL Clock Enable
Enables the PLL independent of PLLS and enables the PLL clock for use as MCGPLLCLK. (PRDIV 0
needs to be programmed to the correct divider to generate a PLL reference clock in the range of 2 - 4
MHz range prior to setting the PLLCLKEN 0 bit). Setting PLLCLKEN 0 will enable the external oscillator if
not already enabled. Whenever the PLL is being enabled by means of the PLLCLKEN 0 bit, and the
external oscillator is being used as the reference clock, the OSCINIT 0 bit should be checked to make
sure it is set.
Table continues on the next page...
Memory Map/Register Definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
436 Freescale Semiconductor, Inc.