Information

24.3.7 MCG Status Register (MCG_S)
Address: MCG_S is 4006_4000h base + 6h offset = 4006_4006h
Bit 7 6 5 4 3 2 1 0
Read LOLS0 LOCK0 PLLST IREFST CLKST OSCINIT0 IRCST
Write
Reset
0 0 0 1 0 0 0 0
MCG_S field descriptions
Field Description
7
LOLS0
Loss of Lock Status
This bit is a sticky bit indicating the lock status for the PLL. LOLS 0 is set if after acquiring lock, the PLL
output frequency has fallen outside the lock exit frequency tolerance, D
unl
. LOLIE 0 determines whether
an interrupt request is made when LOLS 0 is set. LOLRE determines whether a reset request is made
when LOLS0 is set. This bit is cleared by reset or by writing a logic 1 to it when set. Writing a logic 0 to
this bit has no effect.
0 PLL has not lost lock since LOLS 0 was last cleared.
1 PLL has lost lock since LOLS 0 was last cleared.
6
LOCK0
Lock Status
This bit indicates whether the PLL has acquired lock. Lock detection is disabled when not operating in
either PBE or PEE mode unless PLLCLKEN 0 =1 and the MCG is not configured in BLPI or BLPE mode.
While the PLL clock is locking to the desired frequency, the MCG PLL clock (MCGPLLCLK) will be gated
off until the LOCK 0 bit gets asserted. If the lock status bit is set, changing the value of the PRDIV 0 [4:0]
bits in the C5 register or the VDIV0[4:0] bits in the C6 register causes the lock status bit to clear and stay
cleared until the PLL has reacquired lock. Loss of PLL reference clock will also cause the LOCK 0 bit to
clear until PLL has reacquired lock. Entry into LLS, VLPS, or regular Stop with PLLSTEN 0 =0 also
causes the lock status bit to clear and stay cleared until the Stop mode is exited and the PLL has
reacquired lock. Any time the PLL is enabled and the LOCK 0 bit is cleared, the MCGPLLCLK will be
gated off until the LOCK 0 bit is asserted again.
0 PLL is currently unlocked.
1 PLL is currently locked.
5
PLLST
PLL Select Status
This bit indicates the clock source selected by PLLS . The PLLST bit does not update immediately after a
write to the PLLS bit due to internal synchronization between clock domains.
0 Source of PLLS clock is FLL clock.
1
Source of PLLS clock is PLL clock.
4
IREFST
Internal Reference Status
This bit indicates the current source for the FLL reference clock. The IREFST bit does not update
immediately after a write to the IREFS bit due to internal synchronization between clock domains.
0 Source of FLL reference clock is the external reference clock.
1 Source of FLL reference clock is the internal reference clock.
Table continues on the next page...
Chapter 24 Multipurpose Clock Generator (MCG)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 439