Information

27.1.2 Features
The FMC's features include:
• Interface between the device and the flash memory and FlexMemory:
• 8-bit, 16-bit, and 32-bit read operations to program flash memory and FlexNVM
used as data flash memory.
• 8-bit, 16-bit, and 32-bit read and write operations to FlexNVM and FlexRAM
used as EEPROM.
• Read accesses to consecutive 32-bit spaces in memory return the second read
data with no wait states. The memory returns 32 bits via the 32-bit bus access.
• Crossbar master access protection for setting no access, read only access, write
only access, or read/write access for each crossbar master.
• Acceleration of data transfer from program flash memory and FlexMemory to the
device:
• 32-bit prefetch speculation buffer with controls for instruction/data access per
master
• 4-way, 2-set, 32-bit line size cache for a total of eight 32-bit entries with controls
for replacement algorithm and lock per way
• Single-entry buffer with enable
• Invalidation control for the speculation buffer and the single-entry buffer
27.2 Modes of operation
The FMC only operates when the device accesses the flash memory or FlexMemory.
In terms of device power modes, the FMC only operates in run and wait modes, including
VLPR and VLPW modes.
For any device power mode where the flash memory or FlexMemory cannot be accessed,
the FMC is disabled.
27.3 External signal description
The FMC has no external signals.
Modes of operation
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
482 Freescale Semiconductor, Inc.