Information

FMC_PFAPR field descriptions (continued)
Field Description
15–8
Reserved
This field is reserved.
7–6
M3AP[1:0]
Master 3 Access Protection
This field controls whether read and write access to the flash are allowed based on the logical master
number of the requesting crossbar switch master.
00 No access may be performed by this master
01 Only read accesses may be performed by this master
10 Only write accesses may be performed by this master
11 Both read and write accesses may be performed by this master
5–4
M2AP[1:0]
Master 2 Access Protection
This field controls whether read and write access to the flash are allowed based on the logical master
number of the requesting crossbar switch master.
00 No access may be performed by this master
01 Only read accesses may be performed by this master
10 Only write accesses may be performed by this master
11 Both read and write accesses may be performed by this master
3–2
M1AP[1:0]
Master 1 Access Protection
This field controls whether read and write access to the flash are allowed based on the logical master
number of the requesting crossbar switch master.
00 No access may be performed by this master
01 Only read accesses may be performed by this master
10 Only write accesses may be performed by this master
11 Both read and write accesses may be performed by this master
1–0
M0AP[1:0]
Master 0 Access Protection
This field controls whether read and write access to the flash are allowed based on the logical master
number of the requesting crossbar switch master.
00 No access may be performed by this master
01 Only read accesses may be performed by this master
10 Only write accesses may be performed by this master
11 Both read and write accesses may be performed by this master
Memory map and register descriptions
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
486 Freescale Semiconductor, Inc.