Information

FMC_PFB0CR field descriptions (continued)
Field Description
1
B0IPE
Instruction Prefetch Enable
This bit controls whether prefetches (or speculative accesses) are initiated in response to instruction
fetches.
0 Do not prefetch in response to instruction fetches.
1 Enable prefetches in response to instruction fetches.
0
B0SEBE
Single Entry Buffer Enable
This bit controls whether the single entry page buffer is enabled in response to flash read accesses.
A high-to-low transition of this enable forces the page buffer to be invalidated.
0 Single entry buffer is disabled.
1 Single entry buffer is enabled.
27.4.3 Cache Tag Storage (FMC_TAGVDW0Sn)
The 32-entry cache is a 4-way, set-associative cache with 2 sets. The ways are numbered
0-3 and the sets are numbered 0-1. In TAGVDWxSy, x denotes the way, and y denotes
the set. This section represents tag/vld information for the 2 sets (n=0-1) in way 0.
Addresses: TAGVDW0S0 is 4001_F000h base + 100h offset = 4001_F100h
TAGVDW0S1 is 4001_F000h base + 104h offset = 4001_F104h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
tag[18:6]
0
valid
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FMC_TAGVDW0Sn field descriptions
Field Description
31–19
Reserved
This read-only field is reserved and always has the value zero.
18–6
tag[18:6]
13-bit tag for cache entry
5–1
Reserved
This read-only field is reserved and always has the value zero.
0
valid
1-bit valid for cache entry
Chapter 27 Flash Memory Controller (FMC)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 489