Information

27.4.4 Cache Tag Storage (FMC_TAGVDW1Sn)
The 32-entry cache is a 4-way, set-associative cache with 2 sets. The ways are numbered
0-3 and the sets are numbered 0-1. In TAGVDWxSy, x denotes the way, and y denotes
the set. This section represents tag/vld information for the 2 sets (n=0-1) in way 1.
Addresses: TAGVDW1S0 is 4001_F000h base + 108h offset = 4001_F108h
TAGVDW1S1 is 4001_F000h base + 10Ch offset = 4001_F10Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
tag[18:6]
0
valid
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FMC_TAGVDW1Sn field descriptions
Field Description
31–19
Reserved
This read-only field is reserved and always has the value zero.
18–6
tag[18:6]
13-bit tag for cache entry
5–1
Reserved
This read-only field is reserved and always has the value zero.
0
valid
1-bit valid for cache entry
27.4.5 Cache Tag Storage (FMC_TAGVDW2Sn)
The 32-entry cache is a 4-way, set-associative cache with 2 sets. The ways are numbered
0-3 and the sets are numbered 0-1. In TAGVDWxSy, x denotes the way, and y denotes
the set. This section represents tag/vld information for the 2 sets (n=0-1) in way 2.
Addresses: TAGVDW2S0 is 4001_F000h base + 110h offset = 4001_F110h
TAGVDW2S1 is 4001_F000h base + 114h offset = 4001_F114h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
tag[18:6]
0
valid
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Memory map and register descriptions
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
490 Freescale Semiconductor, Inc.