Information

FTFL_FSTAT field descriptions (continued)
Field Description
error by the block arbitration logic. The read data in this case cannot be guaranteed. The RDCOLERR bit
is cleared by writing a 1 to it. Writing a 0 to RDCOLERR has no effect.
0 No collision error detected
1 Collision error detected
5
ACCERR
Flash Access Error Flag
The ACCERR error bit indicates an illegal access has occurred to a flash memory resource caused by a
violation of the command write sequence or issuing an illegal flash command. While ACCERR is set, the
CCIF flag cannot be cleared to launch a command. The ACCERR bit is cleared by writing a 1 to it. Writing
a 0 to the ACCERR bit has no effect.
0 No access error detected
1 Access error detected
4
FPVIOL
Flash Protection Violation Flag
The FPVIOL error bit indicates an attempt was made to program or erase an address in a protected area
of program flash or data flash memory during a command write sequence or a write was attempted to a
protected area of the FlexRAM while enabled for EEPROM . While FPVIOL is set, the CCIF flag cannot
be cleared to launch a command. The FPVIOL bit is cleared by writing a 1 to it. Writing a 0 to the FPVIOL
bit has no effect.
0 No protection violation detected
1 Protection violation detected
3–1
Reserved
This read-only field is reserved and always has the value zero.
0
MGSTAT0
Memory Controller Command Completion Status Flag
The MGSTAT0 status flag is set if an error is detected during execution of a flash command or during the
flash reset sequence. As a status flag, this bit cannot (and need not) be cleared by the user like the other
error flags in this register.
The value of the MGSTAT0 bit for "command-N" is valid only at the end of the "command-N" execution
when CCIF=1 and before the next command has been launched. At some point during the execution of
"command-N+1," the previous result is discarded and any previous error is cleared.
28.34.2 Flash Configuration Register (FTFL_FCNFG)
This register provides information on the current functional state of the flash memory
module.
The erase control bits (ERSAREQ and ERSSUSP) have write restrictions. PFLSH,
RAMRDY, and EEERDYare read-only status bits . The unassigned bits read as noted and
are not writable. The reset values for the PFLASH, RAMRDY, and EEERDY bits are
determined during the reset sequence.
Chapter 28 Flash Memory Module (FTFL)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 507