Information

FTFL_FEPROT field descriptions (continued)
Field Description
Reset: During the reset sequence, the FEPROT register is loaded with the contents of the FlexRAM
protection byte in the Flash Configuration Field located in program flash. The flash basis for the reset
values is signified by X in the register diagram. To change the EEPROM protection that will be loaded
during the reset sequence, the sector of program flash that contains the Flash Configuration Field must be
unprotected; then the EEPROM protection byte must be erased and reprogrammed.
Trying to alter data by writing to any protected area in the EEPROM results in a protection violation error
and sets the FPVIOL bit in the FSTAT register.
0 EEPROM region is protected
1 EEPROM region is not protected
28.34.8 Data Flash Protection Register (FTFL_FDPROT)
The FDPROT register defines which data flash regions are protected against program and
erase operations. Protected Flash regions cannot have their content changed; that is, these
regions cannot be programmed and cannot be erased by any flash command. Unprotected
regions can be changed by both program and erase operations.
Address: FTFL_FDPROT is 4002_0000h base + 17h offset = 4002_0017h
Bit 7 6 5 4 3 2 1 0
Read
DPROT
Write
Reset
x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset.•
FTFL_FDPROT field descriptions
Field Description
7–0
DPROT
Data Flash Region Protect
Individual data flash regions can be protected from program and erase operations by setting the
associated DPROT bit. Each DPROT bit protects one-eighth of the partitioned data flash memory space.
The granularity of data flash protection cannot be less than the data flash sector size. If an unused
DPROT bit is set, the Erase all Blocks command does not execute and the FSTAT[FPVIOL] flag is set.
In NVM Normal mode: The protection can only be increased, meaning that currently unprotected
memory can be protected but currently protected memory cannot be unprotected. Since unprotected
regions are marked with a 1 and protected regions use a 0, only writes changing 1s to 0s are accepted.
This 1-to-0 transition check is performed on a bit-by-bit basis. Those FDPROT bits with 1-to-0 transitions
are accepted while all bits with 0-to-1 transitions are ignored .
In NVM Special mode: All bits of the FDPROT register are writable without restriction. Unprotected areas
can be protected and protected areas can be unprotected.
Restriction: The user must never write to the FDPROT register while a command is running (CCIF=0).
Chapter 28 Flash Memory Module (FTFL)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 515