Information

Table 2-2. Core modules (continued)

Module Description

NVIC The ARMv7-M exception model and nested-vectored interrupt controller (NVIC)

implement a relocatable vector table supporting many external interrupts, a single

non-maskable interrupt (NMI), and priority levels.

The NVIC replaces shadow registers with equivalent system and simplified

programmability. The NVIC contains the address of the function to execute for a

particular handler. The address is fetched via the instruction port allowing parallel

internal sources with the others mapping to MCU-defined interrupts.

AWIC The primary function of the Asynchronous Wake-up Interrupt Controller (AWIC) is

to detect asynchronous wake-up events in stop modes and signal to clock control

logic to resume system clocking. After clock restart, the NVIC observes the

pending interrupt and performs the normal interrupt or event processing.

Debug interfaces Most of this device's debug is based on the ARM CoreSight

™

architecture. Four

debug interfaces are supported:

• IEEE 1149.1 JTAG

• IEEE 1149.7 JTAG (cJTAG)

• Serial Wire Debug (SWD)

• ARM Real-Time Trace Interface

2.4.2 System Modules

The following system modules are available on this device.

Table 2-3. System modules

Module Description

System integration module (SIM) The SIM includes integration logic and several module configuration settings.

System mode controller The SMC provides control and protection on entry and exit to each power mode,

control for the Power management controller (PMC), and reset entry and exit for

the complete MCU.

Power management controller (PMC) The PMC provides the user with multiple power options. Ten different modes are

supported that allow the user to optimize power consumption for the level of

functionality needed. Includes power-on-reset (POR) and integrated low voltage

detect (LVD) with reset (brownout) capability and selectable LVD trip points.

Low-leakage wakeup unit (LLWU) The LLWU module allows the device to wake from low leakage power modes (LLS

and VLLS) through various internal peripheral and external pin sources.

Miscellaneous control module (MCM) The MCM includes integration logic and embedded trace buffer details.

Crossbar switch (XBS) The XBS connects bus masters and bus slaves, allowing all bus masters to

access different bus slaves simultaneously and providing arbitration among the

bus masters when they access the same slave.

Peripheral bridges The peripheral bridge converts the crossbar switch interface to an interface to

access a majority of peripherals on the device.

DMA multiplexer (DMAMUX) The DMA multiplexer selects from many DMA requests down to a smaller number

for the DMA controller.

Table continues on the next page...

Module Functional Categories

K20 Sub-Family Reference Manual, Rev. 2, Feb 2012

52 Freescale Semiconductor, Inc.