Information

Figure 28-31. EEPROM backup writes to FlexRAM
28.4.3 Interrupts
The flash memory module can generate interrupt requests to the MCU upon the
occurrence of various flash events. These interrupt events and their associated status and
control bits are shown in the following table.
Table 28-30. Flash Interrupt Sources
Flash Event Readable
Status Bit
Interrupt
Enable Bit
Flash Command Complete FSTAT[CCIF] FCNFG[CCIE]
Flash Read Collision Error FSTAT[RDCOLERR] FCNFG[RDCOLLIE]
Note
Vector addresses and their relative interrupt priority are
determined at the MCU level.
Functional Description
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
522 Freescale Semiconductor, Inc.