Information

31.3.16 ADC plus-side general calibration value register
(ADCx_CLP1)
For more information, refer to CLPD register description.
Addresses: ADC0_CLP1 is 4003_B000h base + 48h offset = 4003_B048h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CLP1
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
ADCx_CLP1 field descriptions
Field Description
31–7
Reserved
This read-only field is reserved and always has the value zero.
6–0
CLP1
Calibration value
31.3.17 ADC plus-side general calibration value register
(ADCx_CLP0)
For more information, refer to CLPD register description.
Addresses: ADC0_CLP0 is 4003_B000h base + 4Ch offset = 4003_B04Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CLP0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
ADCx_CLP0 field descriptions
Field Description
31–6
Reserved
This read-only field is reserved and always has the value zero.
5–0
CLP0
Calibration value
Chapter 31 Analog-to-Digital Converter (ADC)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 601