Information

31.3.18 ADC minus-side general calibration value register
(ADCx_CLMD)
CLMx contain calibration information that is generated by the calibration function. These
registers contain seven calibration values of varying widths: CLM0[5:0], CLM1[6:0],
CLM2[7:0], CLM3[8:0], CLM4[9:0], CLMS[5:0], and CLMD[5:0]. CLMx are
automatically set once the self calibration sequence is done (CAL is cleared). If these
registers are written by the user after calibration, the linearity error specifications may not
be met.
Addresses: ADC0_CLMD is 4003_B000h base + 54h offset = 4003_B054h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CLMD
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
ADCx_CLMD field descriptions
Field Description
31–6
Reserved
This read-only field is reserved and always has the value zero.
5–0
CLMD
Calibration value
31.3.19 ADC minus-side general calibration value register
(ADCx_CLMS)
For more information, refer to CLMD register description.
Addresses: ADC0_CLMS is 4003_B000h base + 58h offset = 4003_B058h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CLMS
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
ADCx_CLMS field descriptions
Field Description
31–6
Reserved
This read-only field is reserved and always has the value zero.
5–0
CLMS
Calibration value
Register Definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
602 Freescale Semiconductor, Inc.