Information

31.3.24 ADC minus-side general calibration value register

(ADCx_CLM0)

For more information, refer to CLMD register description.

Addresses: ADC0_CLM0 is 4003_B000h base + 6Ch offset = 4003_B06Ch

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CLM0

Reset

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0

ADCx_CLM0 field descriptions

Field Description

31–6

Reserved

This read-only field is reserved and always has the value zero.

5–0

CLM0

Calibration value

31.4 Functional description

The ADC module is disabled during reset, in low power stop mode (refer to the Power

Management information for details), or when the ADCH bits in SC1n are all high. The

module is idle when a conversion has completed and another conversion has not been

initiated. When it is idle and the asynchronous clock output enable is disabled

(ADACKEN is 0), the module is in its lowest power state. The ADC can perform an

analog-to-digital conversion on any of the software selectable channels. All modes

perform conversion by a successive approximation algorithm.

To meet accuracy specifications, the ADC module must be calibrated using the on chip

calibration function. See Calibration function for details on how to perform calibration.

When the conversion is completed, the result is placed in the data registers (Rn). The

respective conversion complete flag (COCO) is then set and an interrupt is generated if

the respective conversion complete interrupt has been enabled (AIEN=1).

The ADC module has the capability of automatically comparing the result of a

conversion with the contents of the compare value registers. The compare function is

enabled by setting the ACFE bit and operates with any of the conversion modes and

configurations.

Chapter 31 Analog-to-Digital Converter (ADC)

K20 Sub-Family Reference Manual, Rev. 2, Feb 2012

Freescale Semiconductor, Inc. 605