Information

31.4.4.6 Conversion time examples
The following examples use Figure 31-62 and the information provided in Table 31-70
through Table 31-74.
31.4.4.6.1 Typical conversion time configuration
A typical configuration for ADC conversion is: 10-bit mode, with the bus clock selected
as the input clock source, the input clock divide-by-1 ratio selected, and a bus frequency
of 8 MHz, long sample time disabled and high speed conversion disabled. The
conversion time for a single conversion is calculated by using Figure 31-62 and the
information provided in Table 31-70 through Table 31-74. The table below list the
variables of Figure 31-62.
Table 31-75. Typical conversion time
Variable Time
SFCAdder 5 ADCK cycles + 5 bus clock cycles
AverageNum 1
BCT 20 ADCK cycles
LSTAdder 0
HSCAdder 0
The resulting conversion time is generated using the parameters listed in the proceeding
table. Therefore, for a bus clock equal to 8 MHz and an ADCK equal to 8 MHz the
resulting conversion time is 3.75 µs.
31.4.4.6.2 Long conversion time configuration
A configuration for long ADC conversion is: 16-bit differential mode with the bus clock
selected as the input clock source, the input clock divide-by-8 ratio selected, a bus
frequency of 8 MHz, long sample time enabled, configured for longest adder, high speed
conversion disabled, and average enabled for 32 conversions. The conversion time for
this conversion is calculated by using Figure 31-62 and the information provided in Table
31-70 through Table 31-74. The following table lists the variables of the Figure 31-62.
Table 31-76. Typical conversion time
Variable Time
SFCAdder 3 ADCK cycles + 5 bus clock cycles
AverageNum 32
BCT 34 ADCK cycles
LSTAdder 20 ADCK cycles
Table continues on the next page...
Chapter 31 Analog-to-Digital Converter (ADC)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 613