Information

32.7.1 CMP Control Register 0 (CMPx_CR0)
Addresses: CMP0_CR0 is 4007_3000h base + 0h offset = 4007_3000h
CMP1_CR0 is 4007_3008h base + 0h offset = 4007_3008h
Bit 7 6 5 4 3 2 1 0
Read 0
FILTER_CNT
0 0
HYSTCTR
Write
Reset
0 0 0 0 0 0 0 0
CMPx_CR0 field descriptions
Field Description
7
Reserved
This read-only field is reserved and always has the value zero.
6–4
FILTER_CNT
Filter Sample Count
Represents the number of consecutive samples that must agree prior to the comparator ouput filter
accepting a new output state. For information regarding filter programming and latency, see the CMP
functional description.
000 Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not
recommended. If SE = 0, COUT = COUTA.
001 One sample must agree. The comparator output is simply sampled.
010 2 consecutive samples must agree.
011 3 consecutive samples must agree.
100 4 consecutive samples must agree.
101 5 consecutive samples must agree.
110 6 consecutive samples must agree.
111 7 consecutive samples must agree.
3
Reserved
This read-only field is reserved and always has the value zero.
2
Reserved
This read-only field is reserved and always has the value zero.
1–0
HYSTCTR
Comparator hard block hysteresis control
Defines the programmable hysteresis level. The hysteresis values associated with each level are device-
specific. See the Data Sheet of the device for the exact values.
00 Level 0
01 Level 1
10 Level 2
11 Level 3
Chapter 32 Comparator (CMP)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 637