Information

Asynchronous
Wake-up Interrupt
Controller (AWIC)
Nested vectored
interrupt controller
(NVIC)
Wake-up
requests
Module
Module
Clock logic
Figure 3-3. Asynchronous Wake-up Interrupt Controller configuration
Table 3-6. Reference links to related information
Topic Related module Reference
System memory map System memory map
Clocking Clock distribution
Power management Power management
Nested Vectored
Interrupt Controller
(NVIC)
NVIC
Wake-up requests AWIC wake-up sources
3.2.3.1 Wake-up sources
The device uses the following internal and external inputs to the AWIC module.
Table 3-7. AWIC Stop and VLPS Wake-up Sources
Wake-up source Description
Available system resets RESET pin and WDOG when LPO is its clock source, and JTAG
Low-voltage detect Mode Controller
Low-voltage warning Mode Controller
Pin interrupts Port Control Module - Any enabled pin interrupt is capable of waking the system
ADCx The ADC is functional when using internal clock source
CMPx Since no system clocks are available, functionality is limited
I
2
C Address match wakeup
UART Active edge on RXD
USB Wakeup
LPTMR Functional in Stop/VLPS modes
RTC Functional in Stop/VLPS modes
I2S Functional when using an external bit clock or external master clock
TSI
Chapter 3 Chip Configuration
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 67