Information

PDBx_CNT field descriptions
Field Description
31–16
Reserved
This read-only field is reserved and always has the value zero.
15–0
CNT
PDB Counter
These read-only bits contain the current value of the counter.
34.3.4 Interrupt Delay Register (PDBx_IDLY)
Addresses: PDB0_IDLY is 4003_6000h base + Ch offset = 4003_600Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
IDLY
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
PDBx_IDLY field descriptions
Field Description
31–16
Reserved
This read-only field is reserved and always has the value zero.
15–0
IDLY
PDB Interrupt Delay
These bits specify the delay value to schedule the PDB interrupt. It can be used to schedule an
independent interrupt at some point in the PDB cycle. If enabled, a PDB interrupt is generated, when the
counter is equal to the IDLY. Reading these bits returns the value of internal register that is effective for
the current cycle of the PDB.
34.3.5 Channel n Control Register 1 (PDBx_CHC1)
Each PDB channel has one Control Register, CHnC1. The bits in this register control the
functionality of each PDB channel operation.
Addresses: PDB0_CH0C1 is 4003_6000h base + 10h offset = 4003_6010h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
BB TOS EN
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_CHnC1 field descriptions
Field Description
31–24
Reserved
This read-only field is reserved and always has the value zero.
Table continues on the next page...
Memory Map and Register Definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
676 Freescale Semiconductor, Inc.