Information

PDBx_CHnS field descriptions (continued)
Field Description
7–0
ERR
PDB Channel Sequence Error Flags
Only the lower M bits are implemented in this MCU.
0 Sequence error not detected on PDB channel's corresponding pre-trigger.
1 Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered
for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by
one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's
corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 1’s to clear the
sequence error flags.
34.3.7 Channel n Delay 0 Register (PDBx_CHDLY0)
Addresses: PDB0_CH0DLY0 is 4003_6000h base + 18h offset = 4003_6018h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
DLY
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_CHnDLY0 field descriptions
Field Description
31–16
Reserved
This read-only field is reserved and always has the value zero.
15–0
DLY
PDB Channel Delay
These bits specify the delay value for the channel's corresponding pre-trigger. The pre-trigger asserts
when the counter is equal to DLY. Reading these bits returns the value of internal register that is effective
for the current PDB cycle.
34.3.8 Channel n Delay 1 Register (PDBx_CHDLY1)
Addresses: PDB0_CH0DLY1 is 4003_6000h base + 1Ch offset = 4003_601Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
DLY
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_CHnDLY1 field descriptions
Field Description
31–16
Reserved
This read-only field is reserved and always has the value zero.
Table continues on the next page...
Memory Map and Register Definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
678 Freescale Semiconductor, Inc.