Information

34.4.2 PDB Trigger Input Source Selection
The PDB has up to 15 trigger input sources, namely Trigger-In 0 to 14. They are
connected to on-chip or off-chip event sources. The PDB can be triggered by software
through the SC[SWTRIG]. SC[TRIGSEL] bits select the active trigger input source or
software trigger.
For the trigger input sources implemented in this MCU, refer to Chip Configuration
information.
34.4.3 Pulse-Out's
PDB can generate pulse outputs of configurable width. When PDB counter reaches the
value set in POyDLY[DLY1], the Pulse-Out goes high; when the counter reaches
POyDLY[DLY2], it goes low. POyDLY[DLY2] can be set either greater or less than
POyDLY[DLY1].
Because the PDB counter is shared by both ADC pre-trigger/trigger outputs and Pulse-
Out generation, they have the same time base.
The pulse-out connections implemented in this MCU are described in the device's Chip
Configuration details.
34.4.4 Updating the Delay Registers
The following registers control the timing of the PDB operation; and in some of the
applications, they may need to become effective at the same time.
• PDB Modulus Register (MOD)
• PDB Interrupt Delay Register (IDLY)
• PDB Channel n Delay m Register (CHnDLYm)
• DAC Interval x Register (DACINTx)
• PDB Pulse-Out y Delay Register (POyDLY)
The internal registers of them are buffered and any values written to them are written first
to their buffers. The circumstances that cause their internal registers to be updated with
the values from the buffers are summarized as below table.
Functional Description
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
682 Freescale Semiconductor, Inc.