Information

3.3.6.3 PRS register reset values
The AXBS_PRSn registers reset to 0000_3210h.
3.3.7 Peripheral Bridge Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Peripherals
Transfers
AIPS-Lite
peripheral bridge
Transfers
Crossbar switch
Figure 3-11. Peripheral bridge configuration
Table 3-16. Reference links to related information
Topic Related module Reference
Full description Peripheral bridge
(AIPS-Lite)
Peripheral bridge (AIPS-Lite)
System memory map System memory map
Clocking Clock Distribution
Crossbar switch Crossbar switch Crossbar switch
3.3.7.1 Number of peripheral bridges
This device contains one peripheral bridge.
3.3.7.2 Memory maps
The peripheral bridges are used to access the registers of most of the modules on this
device. See AIPS0 Memory Map for the memory slot assignment for each module.
3.3.8 DMA request multiplexer configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Chapter 3 Chip Configuration
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 75