Information

Table 3-18. DMA request sources - MUX 0 (continued)
Source
number
Source module Source description
42 CMP0 —
43 CMP1 —
44 Reserved —
45 Reserved —
46 Reserved —
47 CMT —
48 PDB —
49 Port control module Port A
50 Port control module Port B
51 Port control module Port C
52 Port control module Port D
53 Port control module Port E
54 DMA MUX Always enabled
55 DMA MUX Always enabled
56 DMA MUX Always enabled
57 DMA MUX Always enabled
58 DMA MUX Always enabled
59 DMA MUX Always enabled
60 DMA MUX Always enabled
61 DMA MUX Always enabled
62 DMA MUX Always enabled
63 DMA MUX Always enabled
1. Configuring a DMA channel to select source 0 or any of the reserved sources disables that DMA channel.
3.3.8.2 DMA transfers via PIT trigger
The PIT module can trigger a DMA transfer on the first four DMA channels. The
assignments are detailed at PIT/DMA Periodic Trigger Assignments .
3.3.9 DMA Controller Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
System modules
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
78 Freescale Semiconductor, Inc.