Information

38.6.5 CMT Output Control Register (CMT_OC)
This register is used to control the IRO signal of the CMT module.
Address: CMT_OC is 4006_2000h base + 4h offset = 4006_2004h
Bit 7 6 5 4
Read
IROL CMTPOL IROPEN
0
Write
Reset
0 0 0 0
Bit
3 2 1 0
Read 0
Write
Reset
0 0 0 0
CMT_OC field descriptions
Field Description
7
IROL
IRO Latch Control
Reads the state of the IRO latch. Writing to IROL changes the state of the IRO signal
when MSC[MCGEN] is cleared and IROPEN is set.
6
CMTPOL
CMT Output Polarity
Controls the polarity of the IRO signal.
0 The IRO signal is active-low.
1
The IRO signal is active-high.
5
IROPEN
IRO Pin Enable
Enables and disables the IRO signal. When the IRO signal is enabled, it is an output
that drives out either the CMT transmitter output or the state of IROL depending on
whether MSC[MCGEN] is set or not. Also, the state of output is either inverted or
non-inverted, depending on the state of CMTPOL. When the IRO signal is disabled, it
is in a high-impedance state and is unable to draw any current. This signal is
disabled during reset.
0 The IRO signal is disabled.
1
The IRO signal is enabled as output.
4–0
Reserved
This read-only field is reserved and always has the value zero.
Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
846 Freescale Semiconductor, Inc.