Information

Primary
prescaler
if_clk_enable
divider_enable
Bus clock
Secondary
prescaler
Figure 38-14. Clock divider block diagram
For compatibility with previous versions of CMT, when bus clock = 8 MHz, the PPS
must be configured to zero. The PPS counter is selected according to the bus clock to
generate an intermediate frequency approximately equal to 8 MHz.
38.7.2 Carrier generator
The carrier generator resolution is 125 ns when operating with an 8 MHz intermediate
frequency signal and the secondary prescaler is set to divide by 1, or, when
MSC[CMTDIV] = 00. The carrier generator can generate signals with periods between
250 ns (4 MHz) and 127.5 μs (7.84 kHz) in steps of 125 ns. The following table shows
the relationship between the clock divide bits and the carrier generator resolution,
minimum carrier generator period, and minimum modulator period.
Table 38-19. Clock divider
Bus clock
(MHz)
MSC[CMTDIV]
Carrier generator
resolution (μs)
Min. carrier generator
period
(μs)
Min.
modulator period
(μs)
8 00 0.125 0.25 1.0
8 01 0.25 0.5 2.0
8 10 0.5 1.0 4.0
8 11 1.0 2.0 8.0
The possible duty cycle options depend upon the number of counts required to complete
the carrier period. For example, 1.6 MHz signal has a period of 625 ns and will therefore
require 5 x 125 ns counts to generate. These counts may be split between high and low
times, so the duty cycles available will be:
• 20% with one high and four low times
• 40% with two high and three low times
• 60% with three high and two low times, and
• 80% with four high and one low time
.
Chapter 38 Carrier Modulator Transmitter (CMT)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 853