Information

RTC_SR field descriptions
Field Description
31–5
Reserved
This read-only field is reserved and always has the value zero.
4
TCE
Time Counter Enable
When time counter is disabled the TSR register and TPR register are writeable, but do not increment.
When time counter is enabled the TSR register and TPR register are not writeable, but increment.
0 Time counter is disabled.
1 Time counter is enabled.
3
Reserved
This read-only field is reserved and always has the value zero.
2
TAF
Time Alarm Flag
Time alarm flag is set when the TAR[TAR] equals the TSR[TSR] and the TSR[TSR] increments. This bit is
cleared by writing the TAR register.
0 Time alarm has not occurred.
1 Time alarm has occurred.
1
TOF
Time Overflow Flag
Time overflow flag is set when the time counter is enabled and overflows. The TSR and TPR do not
increment and read as zero when this bit is set. This bit is cleared by writing the TSR register when the
time counter is disabled.
0 Time overflow has not occurred.
1 Time overflow has occurred and time counter is read as zero.
0
TIF
Time Invalid Flag
The time invalid flag is set on VBAT POR or software reset. The TSR and TPR do not increment and read
as zero when this bit is set. This bit is cleared by writing the TSR register when the time counter is
disabled.
0 Time is valid.
1 Time is invalid and time counter is read as zero.
39.2.7 RTC Lock Register (RTC_LR)
Address: RTC_LR is 4003_D000h base + 18h offset = 4003_D018h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 1
LRL
SRL
CRL
TCL
1
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Register definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
870 Freescale Semiconductor, Inc.