Information

RTC_RAR field descriptions (continued)
Field Description
0 Reads to the lock register are ignored.
1 Reads to the lock register complete as normal.
5
SRR
Status Register Read
Once cleared, this bit is only set by system reset. It is not affected by VBAT POR or software reset.
0 Reads to the status register are ignored.
1 Reads to the status register complete as normal.
4
CRR
Control Register Read
Once cleared, this bit is only set by system reset. It is not affected by VBAT POR or software reset.
0 Reads to the control register are ignored.
1 Reads to the control register complete as normal.
3
TCRR
Time Compensation Register Read
Once cleared, this bit is only set by system reset. It is not affected by VBAT POR or software reset
0 Reads to the time compensation register are ignored.
1 Reads to the time compensation register complete as normal.
2
TARR
Time Alarm Register Read
Once cleared, this bit is only set by system reset. It is not affected by VBAT POR or software reset.
0 Reads to the time alarm register are ignored.
1 Reads to the time alarm register complete as normal.
1
TPRR
Time Prescaler Register Read
Once cleared, this bit is only set by system reset. It is not affected by VBAT POR or software reset.
0 Reads to the time prescaler register are ignored.
1 Reads to the time prescaler register complete as normal.
0
TSRR
Time Seconds Register Read
Once cleared, this bit is only set by system reset. It is not affected by VBAT POR or software reset.
0 Reads to the time seconds register are ignored.
1 Reads to the time seconds register complete as normal.
39.3 Functional description
Chapter 39 Real Time Clock (RTC)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 875