Information

3.7.1.3.1.1 ADC0 Channel Assignment for 48-Pin Package
ADC Channel
(SC1n[ADCH])
Channel Input signal
(SC1n[DIFF]= 1)
Input signal
(SC1n[DIFF]= 0)
00000 DAD0 ADC0_DP0 and ADC0_DM0 ADC0_DP0
00001 DAD1 Reserved Reserved
00010 DAD2 Reserved Reserved
00011 DAD3 Reserved Reserved
00100
1
AD4a Reserved Reserved
00101
1
AD5a Reserved Reserved
00110
1
AD6a Reserved Reserved
00111
1
AD7a Reserved Reserved
00100
1
AD4b Reserved ADC0_SE4b
00101
1
AD5b Reserved ADC0_SE5b
00110
1
AD6b Reserved ADC0_SE6b
00111
1
AD7b Reserved ADC0_SE7b
01000 AD8 Reserved ADC0_SE8
01001 AD9 Reserved ADC0_SE9
01010 AD10 Reserved Reserved
01011 AD11 Reserved Reserved
01100 AD12 Reserved ADC0_SE12
01101 AD13 Reserved ADC0_SE13
01110 AD14 Reserved ADC0_SE14
01111 AD15 Reserved ADC0_SE15
10000 AD16 Reserved Reserved
10001 AD17 Reserved Reserved
10010 AD18 Reserved Reserved
10011 AD19 Reserved ADC0_DM0
10100 AD20 Reserved Reserved
10101 AD21 Reserved Reserved
10110 AD22 Reserved Reserved
10111 AD23 Reserved
11000 AD24 Reserved Reserved
11001 AD25 Reserved Reserved
11010 AD26 Temperature Sensor (Diff) Temperature Sensor (S.E)
11011 AD27 Bandgap (Diff)
2
Bandgap (S.E)
2
11100 AD28 Reserved Reserved
11101 AD29 -VREFH (Diff) VREFH (S.E)
11110 AD30 Reserved VREFL
11111 AD31 Module Disabled Module Disabled
1. ADCx_CFG2[MUXSEL] bit selects between ADCx_SEn channels a and b. Refer to MUXSEL description in ADC chapter
for details.
Connections/Channel Assignment
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
96 Freescale Semiconductor, Inc.