Information

43.1.4.5 Debug Mode
Debug mode is used for system development and debugging. The MCR[FRZ] bit controls
DSPI behavior in the Debug mode:
• If the bit is set, the DSPI stops all serial transfers, when the MCU is in debug mode.
• If the bit is cleared, the MCU debug mode has no effect on the DSPI.
43.2 DSPI signal descriptions
This section provides description of the DSPI signals.
The following table lists the signals that may connect off chip depending on device
implementation.
Table 43-1. DSPI signal descriptions
Signal Description I/O
PCS0/SS Master mode: Peripheral Chip Select 0 output
Slave mode: Slave Select input
I/O
PCS[3:1] Master mode: Peripheral Chip Select 1 – 3
Slave mode: Unused
O
PCS4 Master mode: Peripheral Chip Select 4
Slave mode: Unused
O
SIN Serial Data In I
SOUT Serial Data Out O
SCK Master mode: Serial Clock (output)
Slave mode: Serial Clock (input)
I/O
43.2.1 PCS0/SS — Peripheral Chip Select/Slave Select
In Master mode, the PCS0 signal is an output that selects which slave device the current
transmission is intended for.
In Slave mode, the active low SS signal is an input signal that allows an SPI master to
select the DSPI as the target for transmission.
DSPI signal descriptions
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
960 Freescale Semiconductor, Inc.