Information

SPIx_RSER field descriptions (continued)
Field Description
14
Reserved
This read-only field is reserved and always has the value zero.
13–0
Reserved
This read-only field is reserved and always has the value zero.
43.3.7 DSPI PUSH TX FIFO Register In Master Mode (SPIx_PUSHR)
PUSHR provides the means to write to the TX FIFO. Data written to this register is
transferred to the TX FIFO . 8- or 16-bit write accesses to the Data Field of PUSHR
transfers the 16 bit Data field of PUSHR to the TX FIFO. Write accesses to the
Command Field of PUSHR transfers the 16 bit Command Field of PUSHR to the TX
FIFO. The register structure is different in Master and Slave modes. In Master mode, the
register provides 16-bit command and data to the TX FIFO. In Slave mode, the 16 bit
Command Field of PUSHR is reserved.
A PUSHR Read Operation returns the topmost TX FIFO entry.
When DSPI Module is disabled, any writes to this register will not update the FIFO.
Hence any reads performed during Module disable mode will return the last PUSHR
write performed when Module was enabled.
Addresses: SPI0_PUSHR is 4002_C000h base + 34h offset = 4002_C034h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CONT
CTAS
EOQ
CTCNT
0 0
PCS[5:0] TXDATA
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPIx_PUSHR field descriptions
Field Description
31
CONT
Continuous Peripheral Chip Select Enable
Selects a continuous selection format. The bit is used in SPI Master mode. The bit enables the selected
PCS signals to remain asserted between transfers.
0 Return PCSn signals to their inactive state between transfers.
1 Keep PCSn signals asserted between transfers.
30–28
CTAS
Clock and Transfer Attributes Select
Table continues on the next page...
Chapter 43 SPI (DSPI)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 977