Information

43.3.8 DSPI PUSH TX FIFO Register In Slave Mode
(SPIx_PUSHR_SLAVE)
PUSHR provides the means to write to the TX FIFO. Data written to this register is
transferred to the TX FIFO. Eight- or sixteen-bit write accesses to the Data Field of
PUSHR transfers the 16 bit Data Field of PUSHR to the TX FIFO. The register structure
is different in master and slave modes. The register structure is different in master and
slave modes. In master mode the register provides 16-bit command and data to the TX
FIFO. In slave mode, the 16 bit Command Field of PUSHR is reserved.
Addresses: SPI0_PUSHR_SLAVE is 4002_C000h base + 34h offset = 4002_C034h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
TXDATA
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPIx_PUSHR_SLAVE field descriptions
Field Description
31–16
Reserved
This read-only field is reserved and always has the value zero.
15–0
TXDATA
Transmit Data
Holds SPI data to be transferred according to the associated SPI command.
43.3.9 DSPI POP RX FIFO Register (SPIx_POPR)
POPR is used to read the RX FIFO. Eight- or sixteen-bit read accesses to the POPR have
the same effect on the RX FIFO as 32-bit read accesses. A write to this register will
generate a Transfer Error.
Addresses: SPI0_POPR is 4002_C000h base + 38h offset = 4002_C038h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
RXDATA
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 43 SPI (DSPI)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 979