Information

Signal multiplexing

Module signals

access

CMP

Peripheral

bridge 0

Other peripherals

Figure 3-30. CMP configuration

Table 3-38. Reference links to related information

Topic Related module Reference

Full description Comparator (CMP) Comparator

System memory map System memory map

Clocking Clock distribution

Power management Power management

Signal multiplexing Port control Signal multiplexing

3.7.2.1 CMP input connections

The following table shows the fixed internal connections to the CMP.

Table 3-39. CMP input connections

CMP Inputs CMP0 CMP1

IN0 CMP0_IN0 CMP1_IN0

IN1 CMP0_IN1 CMP1_IN1

IN2 CMP0_IN2 —

IN3 CMP0_IN3 —

IN4 CMP0_IN4 —

IN5 VREF Output/CMP0_IN5 VREF Output/CMP1_IN5

IN6 Bandgap Bandgap

IN7 6b DAC0 Reference 6b DAC1 Reference

3.7.2.2 CMP external references

The 6-bit DAC sub-block supports selection of two references. For this device, the

references are connected as follows:

Chapter 3 Chip Configuration

K20 Sub-Family Reference Manual, Rev. 2, Feb 2012

Freescale Semiconductor, Inc. 99