Information

PCS
Master SIN
SCK (CPOL = 0)
SCK (CPOL = 1)
Master SOUT
t
DT
Figure 43-53. Continuous SCK Timing Diagram (CONT=0)
If the CONT bit in the TX FIFO entry is set, PCS remains asserted between the transfers.
Under certain conditions, SCK can continue with PCS asserted, but with no data being
shifted out of SOUT, that is, SOUT pulled high. This can cause the slave to receive
incorrect data. Those conditions include:
• Continuous SCK with CONT bit set, but no data in the TX FIFO.
• Continuous SCK with CONT bit set and entering Stopped state (refer to Start and
Stop of DSPI transfers).
• Continuous SCK with CONT bit set and entering Stop mode or Module Disable
mode.
The following figure shows timing diagram for Continuous SCK format with Continuous
Selection enabled.
PCS
Master SIN
SCK (CPOL = 0)
SCK (CPOL = 1)
Master SOUT
transfer 1 transfer 2
Figure 43-54. Continuous SCK timing diagram (CONT=1)
Chapter 43 SPI (DSPI)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 995