Information

43.4.8.1 Stop mode (External Stop mode)

The DSPI supports the Stop mode protocol. When a request is made to enter External

Stop mode, the DSPI block acknowledges the request . If a serial transfer is in progress,

the DSPI waits until it reaches the frame boundary before it is ready to have its clocks

shut off . While the clocks are shut off, the DSPI memory-mapped logic is not accessible.

This also puts the DSPI in STOPPED state. The SR[TXRXS] bit is cleared to indicate

STOPPED state. The states of the interrupt and DMA request signals cannot be changed

while in External Stop mode.

43.4.8.2 Module Disable mode

Module Disable mode is a block-specific mode that the DSPI can enter to save power.

Host CPU can initiate the Module Disable mode by setting the MDIS bit in the MCR.

The Module Disable mode can also be initiated by hardware. A power management block

can initiate the Module Disable mode by asserting the DOZE mode signal while the

DOZE bit in the MCR is set.

When the MDIS bit is set or the DOZE mode signal is asserted while the DOZE bit is set,

the DSPI negates Clock Enable signal at the next frame boundary. Once the Clock Enable

signal is negated, DSPI is said to have entered Module Disable Mode. This also puts the

DSPI in STOPPED state. The SR[TXRXS] bit is cleared to indicate STOPPED state.If

implemented, the Clock Enable signal can stop the clock to the non-memory mapped

logic. When Clock Enable is negated, the DSPI is in a dormant state, but the memory

mapped registers are still accessible. Certain read or write operations have a different

effect when the DSPI is in the Module Disable mode. Reading the RX FIFO Pop Register

does not change the state of the RX FIFO. Similarly, writing to the PUSHR Register does

not change the state of the TX FIFO. Clearing either of the FIFOs has no effect in the

Module Disable mode. Changes to the DIS_TXF and DIS_RXF fields of the MCR have

no effect in the Module Disable mode. In the Module Disable mode, all status bits and

effect. Writing to the TCR during Module Disable mode has no effect. Interrupt and

DMA request signals cannot be cleared while in the Module Disable mode.

43.5 Initialization/application information

This section describes how to initialize the DSPI module.

Chapter 43 SPI (DSPI)

K20 Sub-Family Reference Manual, Rev. 2, Feb 2012

Freescale Semiconductor, Inc. 999