Information

Table 22. EzPort switching specifications (continued)
Num Description Min. Max. Unit
EP1 EZP_CK frequency of operation (all commands except
READ)
— f
SYS
/2 MHz
EP1a EZP_CK frequency of operation (READ command) — f
SYS
/8 MHz
EP2 EZP_CS negation to next EZP_CS assertion 2 x t
EZP_CK
— ns
EP3 EZP_CS input valid to EZP_CK high (setup) 5 — ns
EP4 EZP_CK high to EZP_CS input invalid (hold) 5 — ns
EP5 EZP_D input valid to EZP_CK high (setup) 2 — ns
EP6 EZP_CK high to EZP_D input invalid (hold) 5 — ns
EP7 EZP_CK low to EZP_Q output valid — 17 ns
EP8 EZP_CK low to EZP_Q output invalid (hold) 0 — ns
EP9 EZP_CS negation to EZP_Q tri-state — 12 ns
EP2
EP3
EP4
EP5 EP6
EP7
EP8
EP9
EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
Figure 9. EzPort Timing Diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.6 Analog
Peripheral operating requirements and behaviors
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc. 35